csu3_am335x/EVSE/Projects/CCS/dts/linux/[CCS]am335x-evm.dts

/*
 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.

#define PIN_OUTPUT		(PULL_DISABLE)
#define PIN_OUTPUT_PULLUP	(PULL_UP)
#define PIN_OUTPUT_PULLDOWN	0
#define PIN_INPUT		(INPUT_EN | PULL_DISABLE)
#define PIN_INPUT_PULLUP	(INPUT_EN | PULL_UP)
#define PIN_INPUT_PULLDOWN	(INPUT_EN)


 */
/dts-v1/;

#include "am33xx.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	model = "TI AM335x EVM";
	compatible = "ti,am335x-evm", "ti,am33xx";

	cpus {
		cpu@0 {
			cpu0-supply = <&vdd1_reg>;
		};
	};

	memory {
		device_type = "memory";
		/*reg = <0x80000000 0x10000000>;*/ /* 256 MB */
		reg = <0x80000000 0x20000000>; /* 512 MB */ /* +++ vern,512MB DDR ,20181030 ---*/
	};
	/* +++ vern,ramdisk,20181030 +++*/
	chosen {
		bootargs = "console=ttyS0,115200n8 root=/dev/ram0";
	};
	/* --- vern,ramdisk ,20181030 ---*/
	vbat: fixedregulator@0 {
		compatible = "regulator-fixed";
		regulator-name = "vbat";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-boot-on;
	};

	lis3_reg: fixedregulator@1 {
		compatible = "regulator-fixed";
		regulator-name = "lis3_reg";
		regulator-boot-on;
	};
};

/******************** Pin Mux ********************/
&am33xx_pinmux {
	pinctrl-names = "default";
	pinctrl-0 = <&InitialGPIO>;
	pinctrl-1 = <&clkout2_pin>;

	InitialGPIO: InitialGPIO {
		pinctrl-single,pins = <

			/** Offset: 0x800 */
			/** GPIO 0 */
			0x150 (PIN_OUTPUT | MUX_MODE7)	/* SPI0_SCLK.GPIO0_2 */
			0x154 (PIN_INPUT | MUX_MODE7)	/* SPI0_D0.GPIO0_3 */
			0x0D0 (PIN_INPUT | MUX_MODE7)	/* LCD_DATA12.GPIO0_8*/
			0x0D4 (PIN_OUTPUT | MUX_MODE7)	/* LCD_DATA13.GPIO0_9*/
			0x0DC (PIN_OUTPUT | MUX_MODE7)	/* LCD_DATA15.GPIO0_11*/
			0x1B0 (PIN_INPUT | MUX_MODE7)	/* XDMA_EVENT_INTR0.GPIO0_19 */
			0x1B4 (PIN_INPUT | MUX_MODE7)	/* XDMA_EVENT_INTR1.GPIO0_20 */

			/** GPIO 1 */
			0x030 (PIN_INPUT | MUX_MODE7)	/* GPMC_AD12.GPIO1_12*/
			0x034 (PIN_OUTPUT | MUX_MODE7)	/* GPMC_AD13.GPIO1_13*/
			0x038 (PIN_INPUT | MUX_MODE7)	/* GPMC_AD14.GPIO1_14*/
			0x03C (PIN_OUTPUT | MUX_MODE7)	/* GPMC_AD15.GPIO1_15*/
			/*0x078 (PIN_INPUT | MUX_MODE7)	*//* GPMC_BEn1.GPIO1_28*/

			/** GPIO 2 */
			0x088 (PIN_INPUT | MUX_MODE7)	/* CCS (AM_QCA7k_INT, T13)	=>GPMC_CSn3.GPIO2_0*/
			0x0A0 (PIN_OUTPUT | MUX_MODE7)	/* LCD_DATA0.GPIO2_6*/
			0x0AC (PIN_OUTPUT | MUX_MODE7)	/* LCD_DATA3.GPIO2_9*/
			0x0B0 (PIN_OUTPUT | MUX_MODE7)	/* LCD_DATA4.GPIO2_10*/
			0x0B4 (PIN_INPUT | MUX_MODE7)	/* LCD_DATA5.GPIO2_11*/
			0x0B8 (PIN_INPUT | MUX_MODE7)	/* LCD_DATA6.GPIO2_12*/
			0x0BC (PIN_OUTPUT | MUX_MODE7)	/* LCD_DATA7.GPIO2_13*/
			0x0C0 (PIN_OUTPUT | MUX_MODE7)	/* LCD_DATA8.GPIO2_14*/
			0x0C4 (PIN_OUTPUT | MUX_MODE7)	/* LCD_DATA9.GPIO2_15*/
			0x0CC (PIN_OUTPUT | MUX_MODE7)	/* LCD_DATA11.GPIO2_17*/
			0x0E0 (PIN_OUTPUT | MUX_MODE7)	/* CCS (Pilot_state_E, U5)	=>LCD_VSYNC.GPIO2_22*/
			0x0E4 (PIN_INPUT | MUX_MODE7)	/* CCS (AM_IO_1, R5) 		=> LCD_HSYNC.GPIO2_23*/
			0x0E8 (PIN_OUTPUT | MUX_MODE7)	/* CCS (AM_QCA_PWR_RST, V5) => LCD_PCLK.GPIO2_24*/
			0x0EC (PIN_OUTPUT | MUX_MODE7)	/* CCS (AM_IO_2, R6) 		=> LCD_AC_BIAS_EN.GPIO2_25*/

			/** GPIO 3 */
			0x108 (PIN_OUTPUT | MUX_MODE7)	/* MII1_COL.GPIO3_0 */
			0x1A0 (PIN_OUTPUT | MUX_MODE7)	/* MCASP0_ACLKR.GPIO3_18 */
			0x1A4 (PIN_OUTPUT | MUX_MODE7)	/* MCASP0_FSR.GPIO3_19 */
			0x1A8 (PIN_OUTPUT | MUX_MODE7)	/* MCASP0_AXR1.GPIO3_20 */
			/*0x1AC (PIN_INPUT | MUX_MODE7)	*//* CCS (MMC_Card_Det, A14) =>MCASP0_AHCLKX.GPIO3_21 */

		>;
	};

	i2c0_pins: pinmux_i2c0_pins {
		pinctrl-single,pins = <
			0x188 (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c0_sda.i2c0_sda */
			0x18c (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c0_scl.i2c0_scl */
		>;
	};

	i2c1_pins: pinmux_i2c1_pins {
		pinctrl-single,pins = <
			0x158 (PIN_INPUT_PULLUP | MUX_MODE2)	/* spi0_d1.i2c1_sda */
			0x15c (PIN_INPUT_PULLUP | MUX_MODE2)	/* spi0_cs0.i2c1_scl */
		>;
	};

	uart0_pins: pinmux_uart0_pins {
		pinctrl-single,pins = <
			0x170 (PIN_INPUT_PULLUP | MUX_MODE0)	/* uart0_rxd.uart0_rxd */
			0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* uart0_txd.uart0_txd */
		>;
	};

	uart2_pins: pinmux_uart2_pins {
		pinctrl-single,pins = <
			0x10C (PIN_INPUT_PULLUP | MUX_MODE6)	/* MII1_CRS.AM_UART2_RXD */
			0x110 (PIN_OUTPUT_PULLDOWN | MUX_MODE6)	/* MII1_RX_ER.AM_UART2_TXD */
		>;
	};
	#if 0
	uart3_pins: pinmux_uart3_pins {
		pinctrl-single,pins = <
			0x160 (PIN_INPUT_PULLUP | MUX_MODE1)	/* SPI0_CS1.uart3_rxd */
			0x164 (PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* ECAP0_IN_PWM0_OUT.uart3_txd */
		>;
	};
	#endif
	uart4_pins: pinmux_uart4_pins {
		pinctrl-single,pins = <
			0x168 (PIN_INPUT_PULLUP | MUX_MODE1)	/* UART0_CTSn.uart4_rxd */
			0x16C (PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* UART0_RTSn.uart4_txd */
		>;
	};

	uart5_pins: pinmux_uart5_pins {
		pinctrl-single,pins = <
			0x0D8 (PIN_INPUT_PULLUP | MUX_MODE4)	/* LCD_DATA14.UART5_RXD */
			0x144 (PIN_OUTPUT_PULLDOWN | MUX_MODE3)	/* RMII1_REF_CLK.UART5_TXD*/
		>;
	};

	clkout2_pin: pinmux_clkout2_pin {
		pinctrl-single,pins = <
			0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3)	/* xdma_event_intr1.clkout2 */
		>;
	};

	nandflash_pins_default: nandflash_pins_default {
		pinctrl-single,pins = <
			0x0 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad0.gpmc_ad0 */
			0x4 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad1.gpmc_ad1 */
			0x8 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad2.gpmc_ad2 */
			0xc (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad3.gpmc_ad3 */
			0x10 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad4.gpmc_ad4 */
			0x14 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad5.gpmc_ad5 */
			0x18 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad6.gpmc_ad6 */
			0x1c (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad7.gpmc_ad7 */
			0x70 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_wait0.gpmc_wait0 */
			0x74 (PIN_INPUT_PULLUP | MUX_MODE7)	/* gpmc_wpn.gpio0_30 */
			0x7c (PIN_OUTPUT | MUX_MODE0)		/* gpmc_csn0.gpmc_csn0  */
			0x90 (PIN_OUTPUT | MUX_MODE0)		/* gpmc_advn_ale.gpmc_advn_ale */
			0x94 (PIN_OUTPUT | MUX_MODE0)		/* gpmc_oen_ren.gpmc_oen_ren */
			0x98 (PIN_OUTPUT | MUX_MODE0)		/* gpmc_wen.gpmc_wen */
			0x9c (PIN_OUTPUT | MUX_MODE0)		/* gpmc_be0n_cle.gpmc_be0n_cle */
		>;
	};

	nandflash_pins_sleep: nandflash_pins_sleep {
		pinctrl-single,pins = <
			0x0 (PIN_INPUT_PULLDOWN | MUX_MODE7)
			0x4 (PIN_INPUT_PULLDOWN | MUX_MODE7)
			0x8 (PIN_INPUT_PULLDOWN | MUX_MODE7)
			0xc (PIN_INPUT_PULLDOWN | MUX_MODE7)
			0x10 (PIN_INPUT_PULLDOWN | MUX_MODE7)
			0x14 (PIN_INPUT_PULLDOWN | MUX_MODE7)
			0x18 (PIN_INPUT_PULLDOWN | MUX_MODE7)
			0x1c (PIN_INPUT_PULLDOWN | MUX_MODE7)
			0x70 (PIN_INPUT_PULLDOWN | MUX_MODE7)
			0x74 (PIN_INPUT_PULLDOWN | MUX_MODE7)
			0x7c (PIN_INPUT_PULLDOWN | MUX_MODE7)
			0x90 (PIN_INPUT_PULLDOWN | MUX_MODE7)
			0x94 (PIN_INPUT_PULLDOWN | MUX_MODE7)
			0x98 (PIN_INPUT_PULLDOWN | MUX_MODE7)
			0x9c (PIN_INPUT_PULLDOWN | MUX_MODE7)
		>;
	};

	cpsw_default: cpsw_default {
		pinctrl-single,pins = <

			AM33XX_IOPAD(0x878, PIN_INPUT_PULLUP | MUX_MODE1)					/* gpmc_ben1.mii2_col */
			/*AM33XX_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE2)	*/				/* GPMC_CSn3.rmii2_crs_dv*/
			/*AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE1)*/					/* gpmc_wpn.mii2_rxerr */
			AM33XX_IOPAD(0x858, PIN_INPUT_PULLUP | MUX_MODE1)					/* gpmc_a6.mii2_txclk */
			AM33XX_IOPAD(0x85c, PIN_INPUT_PULLUP | MUX_MODE1)					/* gpmc_a7.mii2_rxclk */
			AM33XX_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE1)					/* gpmc_a1.mii2_rxdv */
			AM33XX_IOPAD(0x860, PIN_INPUT_PULLUP | MUX_MODE1)					/* gpmc_a8.mii2_rxd3 */
			AM33XX_IOPAD(0x864, PIN_INPUT_PULLUP | MUX_MODE1)					/* gpmc_a9.mii2_rxd2 */
			AM33XX_IOPAD(0x868, PIN_INPUT_PULLUP | MUX_MODE1)					/* gpmc_a10.mii2_rxd1 */
			AM33XX_IOPAD(0x86c, PIN_INPUT_PULLUP | MUX_MODE1)					/* gpmc_a11.mii2_rxd0 */
			AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE1)				/* gpmc_a0.mii2_txen */
			AM33XX_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE1)				/* gpmc_a2.mii2_txd3 */
			AM33XX_IOPAD(0x84c, PIN_OUTPUT_PULLDOWN | MUX_MODE1)				/* gpmc_a3.mii2_txd2 */
			AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE1)				/* gpmc_a4.mii2_txd1 */
			AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE1)				/* gpmc_a5.mii2_txd0 */

		>;
	};

	cpsw_sleep: cpsw_sleep {
		pinctrl-single,pins = <
			/* Slave 1 reset value */

			/*AM33XX_IOPAD(0x888, PIN_INPUT_PULLDOWN | MUX_MODE7)*/					/* GPMC_CSn3.rmii2_crs_dv*/
			AM33XX_IOPAD(0x840, PIN_INPUT_PULLDOWN | MUX_MODE7)				/* gpmc_a0.mii2_txen */
			AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_a1.mii2_rxdv */
			AM33XX_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7)				/* gpmc_a2.mii2_txd3 */
			AM33XX_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7)			/* gpmc_a3.mii2_txd2 */
			AM33XX_IOPAD(0x850, PIN_INPUT_PULLDOWN | MUX_MODE7)				/* gpmc_a4.mii2_txd1 */
			AM33XX_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7)				/* gpmc_a5.mii2_txd0 */
			AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_a6.mii2_txclk */
			AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_a7.mii2_rxclk */
			AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_a8.mii2_rxd3 */
			AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_a9.mii2_rxd2 */
			AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_a10.mii2_rxd1 */
			AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_a11.mii2_rxd0 */
			/*AM33XX_IOPAD(0x874, PIN_INPUT_PULLDOWN | MUX_MODE7)*/	/* gpmc_wpn.mii2_rxerr */
			AM33XX_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_ben1.mii2_col */

		>;
	};


	davinci_mdio_default: davinci_mdio_default {
		pinctrl-single,pins = <
			/* MDIO */
			0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)	/* mdio_data.mdio_data */
			0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)			/* mdio_clk.mdio_clk */
		>;
	};

	davinci_mdio_sleep: davinci_mdio_sleep {
		pinctrl-single,pins = <
			/* MDIO reset value */
			0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
			0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
		>;
	};

	mmc1_pins_default: pinmux_mmc1_pins {
		pinctrl-single,pins = <
			0x0F0 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc0_dat3.mmc0_dat3 */
			0x0F4 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc0_dat2.mmc0_dat2 */
			0x0F8 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc0_dat1.mmc0_dat1 */
			0x0FC (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc0_dat0.mmc0_dat0 */
			0x100 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc0_clk.mmc0_clk */
			0x104 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mmc0_cmd.mmc0_cmd */
			0x1AC (PIN_INPUT_PULLUP | MUX_MODE7)		/* CCS=>MCASP0_AHCLKX.GPIO3_21 */
		>;
	};

	dcan0_pins_default: dcan0_pins_default {
		pinctrl-single,pins = <
			0x178 (PIN_OUTPUT_PULLUP | MUX_MODE2)			/* uart1_ctsn.d_can0_tx */
			0x17C (PIN_INPUT_PULLDOWN | MUX_MODE2)	/* uart1_rtsn.d_can0_rx */
		>;
	};

	dcan1_pins_default: dcan1_pins_default {
		pinctrl-single,pins = <
			0x180 (PIN_OUTPUT_PULLUP | MUX_MODE2)		/* uart1_rxd.d_can1_tx */
			0x184 (PIN_INPUT_PULLDOWN | MUX_MODE2) 	/* uart1_txd.d_can1_rx */
		>;
	};

	spi1_pins: spi1_pins {
		pinctrl-single,pins = <
			AM33XX_IOPAD(0x990, PIN_INPUT_PULLUP | MUX_MODE3) /* MCASP0_ACLKX.AM_SPI1_SCLK */
			AM33XX_IOPAD(0x994, PIN_INPUT_PULLUP | MUX_MODE3) /* MCASP0_FSX.AM_SPI1_D0 */
			AM33XX_IOPAD(0x998, PIN_OUTPUT_PULLUP | MUX_MODE3) /* MCASP0_AXR0.AM_SPI1_D1 */
			AM33XX_IOPAD(0x99C, PIN_OUTPUT_PULLUP | MUX_MODE3) /* MCASP0_AHCLKR.AM_SPI1_CS0 */
		>;
	};

	ehrpwm1_pins: ehrpwm1_pins {
		pinctrl-single,pins = <
			0x0C8 (PIN_OUTPUT | MUX_MODE2) /* LCD_DATA10.eHRPWM1A */
		>;
	};

	ehrpwm2_pins: ehrpwm2_pins {
		pinctrl-single,pins =<
			0x0A4 (PIN_OUTPUT | MUX_MODE3)	/* LCD_DATA1.eHRPWM2B */
		>;
    };
    ecap0_pins: pinmux_ecap0_pins {
		pinctrl-single,pins = <
			/* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
			AM33XX_IOPAD(0x964, MUX_MODE0)
		>;
	};

	EXTINTn_NMI {
		compatible = "ti, EXTINTn";
		status = "okay";
		interrupt-parent = <&intc>;
		interrupts = <7>;
    };
};



/******************** Peripheral Init ********************/
&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_pins>;

	status = "okay";
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart2_pins>;

	status = "okay";
};
/*
&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart3_pins>;

	status = "okay";
};
*/
&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart4_pins>;

	status = "okay";
};

&uart5 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart5_pins>;

	status = "okay";
};

&i2c0 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_pins>;

	status = "okay";
	clock-frequency = <400000>;

	tps: tps@2d {
		reg = <0x2d>;
	};

	rtc0: rtc@51 {
                compatible = "nxp,pcf85063";
                reg = <0x51>;
        };

};

&i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_pins>;

	status = "okay";
	clock-frequency = <400000>;
};

&usb {
	status = "okay";
};

&usb_ctrl_mod {
	status = "okay";
};

&usb0_phy {
	status = "okay";
};

&usb1_phy {
	status = "okay";
};

&usb0 {
	status = "okay";
};

&usb1 {
	status = "okay";
	dr_mode = "host";
};

&cppi41dma  {
	status = "okay";
};

&elm {
	status = "okay";
};

&epwmss1 {
	status = "okay";

	ehrpwm1: pwm@48302200 {
		status = "okay";
		pinctrl-names = "default";
		pinctrl-0 = <&ehrpwm1_pins>;
	};
};

&epwmss2 {
	status = "okay";

	ehrpwm2: pwm@48304200 {
		status = "okay";
		pinctrl-names = "default";
		pinctrl-0 = <&ehrpwm2_pins>;
	};
};

&gpmc {
	status = "okay";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&nandflash_pins_default>;
	pinctrl-1 = <&nandflash_pins_sleep>;
	/*ranges = <0 0 0x08000000 0x10000000>;*/	/* CS0: NAND */
	ranges = <0 0 0x08000000 0x80000000>;	/*+++ vern,NAND,20181030 ---*/
	nand@0,0 {
		compatible = "ti,omap2-nand";
		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
		interrupt-parent = <&gpmc>;
		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
                    <1 IRQ_TYPE_NONE>;	/* termcount */
		rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
		ti,nand-ecc-opt = "bch8";
		ti,elm-id = <&elm>;
		nand-bus-width = <8>;
		gpmc,device-width = <1>;
		gpmc,sync-clk-ps = <0>;
		gpmc,cs-on-ns = <0>;
		gpmc,cs-rd-off-ns = <44>;
		gpmc,cs-wr-off-ns = <44>;
		gpmc,adv-on-ns = <6>;
		gpmc,adv-rd-off-ns = <34>;
		gpmc,adv-wr-off-ns = <44>;
		gpmc,we-on-ns = <0>;
		gpmc,we-off-ns = <40>;
		gpmc,oe-on-ns = <0>;
		gpmc,oe-off-ns = <54>;
		gpmc,access-ns = <64>;
		gpmc,rd-cycle-ns = <82>;
		gpmc,wr-cycle-ns = <82>;
		gpmc,wait-on-read = "true";
		gpmc,wait-on-write = "true";
		gpmc,bus-turnaround-ns = <0>;
		gpmc,cycle2cycle-delay-ns = <0>;
		gpmc,clk-activation-ns = <0>;
		gpmc,wait-monitoring-ns = <0>;
		gpmc,wr-access-ns = <40>;
		gpmc,wr-data-mux-bus-ns = <0>;
		/* MTD partition table */
		/* All SPL-* partitions are sized to minimal length
		 * which can be independently programmable. For
		 * NAND flash this is equal to size of erase-block */
		#address-cells = <1>;
		#size-cells = <1>;
		partition@0 {
			label = "SPL";
			reg = <0x00000000 0x00080000>;
		};
		partition@1 {
			label = "Primary u-boot";
			reg = <0x00080000 0x00100000>;
		};
		partition@2 {
			label = "u-boot-env";
			reg = <0x00180000 0x00080000>;
		};
		partition@3 {
			label = "Secondary u-boot";
			reg = <0x00200000 0x00100000>;
		};
		partition@4 {
			label = "Primary dtb";
			reg = <0x00300000 0x00080000>;
		};
		partition@5 {
			label = "Secondary dtb";
			reg = <0x00380000 0x00080000>;
		};
		partition@6 {
			label = "Primary kernel";
			reg = <0x00400000 0x00A00000>;
		};
		partition@7 {
			label = "Secondary kernel";
			reg = <0x00E00000 0x00A00000>;
		};
		partition@8 {
			label = "Primary rootfs";
			reg = <0x03000000 0x03000000>;
		};
		partition@9 {
			label = "Secondary rootfs";
			reg = <0x06000000 0x03000000>;
		};
		partition@10 {
			label = "Primary user configuration";
			reg = <0x09000000 0x00600000>;
		};
		partition@11 {
			label = "Secondary user configuration";
			reg = <0x09600000 0x00600000>;
		};
		partition@12 {
			label = "Factory default configuration";
			reg = <0x09C00000 0x00600000>;
		};
		partition@13 {
			label = "Storage";
			reg = <0x0A200000 0x75E00000>;
		};
	};
};

#include "tps65910.dtsi"

&tps {
	vcc1-supply = <&vbat>;
	vcc2-supply = <&vbat>;
	vcc3-supply = <&vbat>;
	vcc4-supply = <&vbat>;
	vcc5-supply = <&vbat>;
	vcc6-supply = <&vbat>;
	vcc7-supply = <&vbat>;
	vccio-supply = <&vbat>;

	regulators {
		vrtc_reg: regulator@0 {
			regulator-always-on;
		};

		vio_reg: regulator@1 {
			regulator-always-on;
		};

		vdd1_reg: regulator@2 {
			/* VDD_MPU voltage limits 0.95V - 1.325V with +/-4% tolerance */
			regulator-name = "vdd_mpu";
			regulator-min-microvolt = <912500>;
			regulator-max-microvolt = <1378000>;
			regulator-boot-on;
			regulator-always-on;
		};

		vdd2_reg: regulator@3 {
			/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
			regulator-name = "vdd_core";
			regulator-min-microvolt = <912500>;
			regulator-max-microvolt = <1150000>;
			regulator-boot-on;
			regulator-always-on;
		};

		vdd3_reg: regulator@4 {
			regulator-always-on;
		};

		vdig1_reg: regulator@5 {
			regulator-always-on;
		};

		vdig2_reg: regulator@6 {
			regulator-always-on;
		};

		vpll_reg: regulator@7 {
			regulator-always-on;
		};

		vdac_reg: regulator@8 {
			regulator-always-on;
		};

		vaux1_reg: regulator@9 {
			regulator-always-on;
		};

		vaux2_reg: regulator@10 {
			regulator-always-on;
		};

		vaux33_reg: regulator@11 {
			regulator-always-on;
		};

		vmmc_reg: regulator@12 {
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <3300000>;
			regulator-always-on;
		};
	};
};

&mac {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&cpsw_default>;
	pinctrl-1 = <&cpsw_sleep>;
	status = "okay";
};

&davinci_mdio {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&davinci_mdio_default>;
	pinctrl-1 = <&davinci_mdio_sleep>;
	status = "okay";
};

&cpsw_emac0 {
	phy_id = <&davinci_mdio>, <1>;
 	phy-mode = "mii";
};



&tscadc {
	status = "okay";
	/*tsc {
		ti,wires = <4>;
		ti,x-plate-resistance = <200>;
		ti,coordinate-readouts = <5>;
		ti,wire-config = <0x00 0x11 0x22 0x33>;
	};*/

	adc {
		ti,adc-channels = <0 1 2 3>;
	};
};


&mmc1 {
	status = "okay";
	vmmc-supply = <&vmmc_reg>;
	bus-width = <4>;
	pinctrl-names = "default";
	pinctrl-0 = <&mmc1_pins_default>;
	cd-gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
};

&edma {
	ti,edma-xbar-event-map = /bits/ 16 <1 12
					    2 13>;
};


&sham {
	status = "okay";
};

&aes {
	status = "okay";
};

&wkup_m3 {
	ti,scale-data-fw = "am335x-evm-scale-data.bin";
};

&dcan0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&dcan0_pins_default>;
};

&dcan1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&dcan1_pins_default>;
};

/*
The QCA7000 acts as a SPI slave and uses Mode 3: CPOL=1, CPHA=1.
SPI data width is 8 bit. The SPI CLK period should not be less than 83.3 ns
The SPI should be used in burst mode, meaning that the chip select is held low during a complete SPI message.
 Note: The SPI lines between Host CPU and QCA7000 should be kept as short as possible.

*/
&spi1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&spi1_pins>;
	qca7000@0 {
		compatible = "qca,qca7000";
		reg = <0>;
		interrupt-parent = <&gpio2>; /* GPIO2_0 */
		interrupts = <0 1>;  			/* GPIO2_0 */
		spi-cpha; 					 /* SPI mode: CPHA=1 */
		spi-cpol; 					 /* SPI mode: CPOL=1 */
		spi-max-frequency = <10000000>;  /* freq: 10MHz */
		qca,legacy-mode = <0>;            /* Burst mode */
	};
};

&epwmss0 {
	status = "okay";

	ecap0: ecap@48300100 {
		status = "okay";
		pinctrl-names = "default";
		pinctrl-0 = <&ecap0_pins>;
	};
};